1. Field of the Invention
The present invention relates to a floating-point division cell in which a partial remainder is divided by a divisor, and, in particular, to a repetitive type floating-point division cell which comprises adding/subtracting units, selectors and divisor generators.
2. Description of Background
Generally, to perform multiplication at a high speed in a multiplier, an algorithm such as a secondary Booth and a Wallace tree is provided. However, the algorithm is not provided in a divider. Therefore, a repetitive type division method is generally utilized in the divider as follows.
In the repetitive type division method, a dividend is first compared with a divisor, and then a multi-divisor which is obtained by multiplying the divisor and a multiple of 2 together is subtracted from or added to the dividend according to a sign accompanying the dividend. As a result, a partial remainder is obtained. Thereafter, the partial remainder is repeatedly subtracted or added by a new multi-divisor to calculate a new partial remainder. Finally, a quotient determined by dividing the dividend by the divisor is obtained in the divider. That is, the above method is the same as a calculation method performed by hand.
On the other hand, the Newton-Raphson method is generally utilized to converge the quotient. However, in the Newton-Raphson method, a first approximation of the quotient is subtracted by a value stored in a read only memory. In addition, multiplication steps are performed to converge the quotient, while the multi-divisor calculated according to the repetitive type division method is obtained by shifting the divisor without performing the multiplication.
Accordingly, the Newton-Raphson method is not superior to the repetitive type division method because the multiplication is required in the Newton-Raphson method. Therefore, the repetitive type division method is considered in this specification rather than the Newton-Raphson method.
A report ("A High Speed Calculation Method for Computers" written by Kai Hwang, translated by Horikoshi in Japan, published by Kindaikagaku Corporation in Japan on Sep. 1, 1980 describes repetitive type calculation methods such as a recovery type division method, a non-recovery type division method, a high radix and non-recovery type division method, and the like.
However, these methods are based upon one common basic method. That is, the circuits used in these methods comprise adding/subtracting units, selectors and the like in common. Therefore, the size of each circuit can be reduced. Moreover, the number of clock signals for synchronizing the operations performed in the adding/subtracting units can be reduced by setting the adding/subtracting units in an array.
Generally, besides a calculation utilizing the above divider, a floating-point representation is often utilized in calculations performed in a computer. The reason is that the range calculated in the computer can be considerably extended. Moreover, several types of floating-point processors have been developed to efficiently perform floating-point calculations.
FIG. 1 is a block diagram of a conventional floating-point division cell, an array of conventional division cells constituting a conventional floating-point divider arranged in a floating-point processor.
As shown in FIG. 1, a conventional floating-point division cell comprises:
a divisor generator 11 for generating a divisor with a sign accompanying a partial remainder; and
a partial remainder generator 12 for generating a multi-divisor obtained by multiplying the divisor generated by the divisor generator 11 and a multiple of 2 together, adding the multi-divisor to the partial remainder or subtracting the multi-divisor from the partial remainder, and generating a new partial remainder.
In the above configuration, the multi-divisor is subtracted from or added to the partial remainder once in each division cell.
Therefore, by utilizing an array of conventional division cells, a dividend is first processed in a first division cell to calculate a first partial remainder. Thereafter, a new partial remainder is obtained in the following division cell. As a result, a quotient is obtained in the final division cell.
In the floating-point processor structured by the above cell, two types of modes--a single-precision mode and a double-precision mode--are generally utilized. Generally, data formed by the double-precision mode has a 64-bit length, while data formed by the single-precision mode has a 32-bit length.
However, in the floating-point method utilizing the single-precision mode, an exponent section and a fraction section are provided in the 32-bit data. Therefore, the precision of the arithmetic in which the fractions are processed is inferior to the precision of a fixed-point arithmetic.
Moreover, in a processor such as a RISC processor in which a pipeline calculation is performed, a calculation not influencing the pipeline is required. However, in cases where an internal bus arranged in the floating-point processor is formed with a prescribed width applicable to the single-precision calculation, an adverse influence is exerted on the pipeline calculation when the double-precision calculation is performed in the floating-point processor.
To prevent the above adverse influence, the internal bus is provided with a large width applicable to double-precision calculations to connect the registers with arithmetical units so that the adverse influence is not exerted on the pipeline calculation performed in the floating-point processor.
In the above floating-point processor with the internal bus applicable to double-precision calculations, in cases where a single-precision calculation is performed, "0" bits are provided in low-order bit fields which are not utilized for the single-precision calculation. Therefore, in the single-precision calculation, half the data is not used so that half of the circuit is not required.